Fundamental Technologies Voyager LECP Pages

Circuit Detail

The PHA can be analyzed using the included block diagrams, timing diagrams and circuit schematics. The following comments are guides to the drawings and diagrams and include a number of unique areas encountered. A prototype tester is available with one set of the basic A/D converter and control boards. As of July 1977 no spare set of Peak Detector boards was available. The test set, test mounts and spare boards are in storage at the S1P electronics laboratory, Howard County, building 4, room 237.

The Pulse Height Analyzer consists of 10 printed circuit boards in the Pulse Circuit Assembly of the Low Energy Charged Particle experiment. The boards include the following:

The 1520, 1530, 1540, and 1550 boards work together as a unit performing analog to digital conversion and multiplexing upon receipt of the experiment GO pulse. The 1560 and 1570 boards work together as five channels of peak detection with no interaction to the rest of the PHA except for power control and the HOLD function.

PHA to Experiment Interface and Control. The 1550 and 1530 boards provide power control, input line buffers, output line drivers and most of the logic necessary for the interface. The detailed block diagram of Figure 2 illustrates the power control structure wherein the major portion of the PHA circuitry stays OFF except during the analog to digital conversion cycle. Also, power to the peak detector and buffer boards (1560 and 1570) is on only when one of the A/D converters is under power and in the LEPT mode.

Power voltages are switched by either of two EME hybrids (0265 and 0274) as designed by D. Fort. These use J-FET switches to achieve efficient power control. Standby power is controlled by a type II (EME 0265) switch hybrid which is minimum power drain but slow switching. Cycled power for the A/D conversion cycle is controlled by a type III (EME-0274) hybrid and two transistors to obtain rapid turn ON (typically less than 3 microseconds) at the start of the cycle. Three types of power distribution are shown in Figure 2, the standby power as dotted voltages, conversion cycle power as "S" voltages, and peak detector circuit power as "P" voltages. In all cases the switch hybrids are turned ON by a positive voltage at the control pin.

The standby circuits of the main electronics are shown as the right hand portion of Figure 2 and are separated from the cycled power blocks by a vertical dashed line. This circuitry must accomplish the following:

PHA Standby Circuit Functions

1. Control power lines
2. Provide master timing for conversion cycle
3. Detect the request for a conversion by the "GO" signal
4. Detect the operating mode from Cal, L/L and D1/D5 inputs
5. Regenerate the 50.4 kHz clock for timing and provide two phases for internal operation
6. Translate the +8 volt external signal levels to the +12 volt digital levels required for the A/D conversion.

Most of the control and interface circuitry is on the 1554 board. The schematic shows the interfaces are accomplished with hex buffers, inverters for the input control lines and non-inverters on the output digital lines. An exception is the clock detection Schmitt-trigger which is designed using three NAND gates. Schmitts were not available for this program. Logic level translation from the internal +12 to the required +8 V output is done directly by the CD4050 buffer. Input level shift from +8 to +12 is more difficult and required transistors Q1 through Q5. The transistor bias circuit for Q1 and Q5 uses a hot-carrier clamp diode (CR-1 and CR-2) to prevent saturation and maintain fast turn-off in the "Go" and "Clk" circuits. The transistor collectors have the same phase as the emitters and switch between about +0.2 V above the drive lower voltage and +12 volts. This logic voltage shaft was done in the interest of using as high a reference voltage as practical (8.000V) to minimize offset errors and noise during the analog to digital conversion.

Interface noise rejection is enhanced by the clock Schmitt-trigger and providing shaped transitions on the output lines. False clock pulses would be a major problem since they could cause internal logic state jumps and pronounced malfunction. Shaping the output transitions both reduces cross coupling in the cabling and minimizes ringing at the receiving end of the lines. The buffer inputs and outputs are all resistor isolated to prevent loading of the experiment Command and Data logic at times the PHA is turned OFF. Note the input lines do not have pull down input resistors and the board must not be operated without being connected to a tester or some other control to prevent excessive current drain in the U1 and U3 integrated circuits.

Conversion cycle control is accomplished by the binaries of the U6, U7 and U8 packages. The "Detailed Circuit Timing Diagram," Figure 5, shows most of the waveforms within the 1554 board.

Conversion Cycle Timing

1. A "Go" pulse (duration greater than 0.2 uSec positive going) arrives at some arbitrary time setting the "Run" binary.
2. "S" voltages are turned ON. The "Set" binary remains at 0 resetting the A/D converter binaries at the desired state as power comes up and the unit normalizes to the start condition.
3. The "delta" binary begins to cycle on the first positive going clock transition after the "Run" binary is set. Its output is clamped to 1 during standby and must transition to 0 and back to 1 to clock the "Set" binary. This generates a minimum of 1 clock time (abt. 20 uSec) delay for the reset of binaries during power turn ON.
4. The "Set" transition from 0 to 1 removes the reset drive to the A/D converter binaries (via the Clamp gate of 1540) and the "A," "B," and "C" master timing divider. The A/D clock (i.e., "Gated Clock") begins to run. (Pin 11 of U-12 on the 1540 board.)
5. The A/D converter cycle is controlled by a 12 step sequence generated by two CD-4017 10 step counters. The most significant bit @ 1 is maintained for the first two gated clock intervals. This allows between 4 and 5 clock periods (nominally 80 to 100 uSeconds) at power ON time to allow all circuits including the reference voltage to settle prior to deciding the most significant bit value. The scheme also provides a three-clock period interval (about 60 uSec) for the multiplexers, amplifiers and comparator to settle when switching inputs for the second, third and fourth measurement.
6. The "Clamp" line of the 1554 board resets all "bit binaries" to 0 except the MSB and both 10 step counters to zero during the converter power ON, "Set binary" low interval described above.
7. The 1554 board "Reset binary" is originally clocked to 0 during the "Set" low interval. The "Gated Clock" steps the U9 10 counter through its 10 step sequence. The positive transition of its "0" step output toggles the "Enable" binary which generates an immediate count to U11. The next positive clock transition after U11 reaches the "2" condition causes the "Reset" binary to go to 1 generating a "Clamp" and resetting both 10 counters back to zero.
8. The positive transition of "Clamp" drives the "A," "B" and "C" master timing chain. The "A" and "B" levels select the multiplexer position (in conjunction with additional experiment inputs). "C" is used to shut down the A/D converter after the fourth channel is finished.
9. Note that several short delays are required in the circuitry to prevent signal "race" problems. These are shown in Figure 2 as circled delta symbols. For example, it is necessary to maintain operation for one clock interval after completion of the fourth data comparison. The fourth positive transition of the "clamp" signal causes the "C" binary to go to Hi, and the output is delayed a fraction of a microsecond to insure the D input to the "Run" binary changes after its phase 1 clock transition, thus requiring one more clock interval prior to conversion power turn off. All logic is stepped in phase 1 clock time; the phase 2 clock is provided to allow gating. Phase 1 is restored at the point of clocking.
10. The "Run" binary remains at 0 until a new "Go" pulse occurs. "S" power lines are OFF. Multiplex power is OFF and the Peak Detector "Hold" is removed. The delta binary is set to 1 and the "Set" binary reset to 0. "A," "B," and "C" are clamped at reset.
11. The "A," "B," "O.T.," "Busy," and "Data" logic levels are supplied to the experiment Command and Data section. "O.T." is the "Output Time" signal indicating good data is present. Note it is offset one clock time from the "A" and "B" multiplex control levels because the data is strobed at the end of each comparator clock interval. This requires an adjustment in the experiment data section to correlate the bits. The "Busy" level indicates a conversion is in progress.
12. The entire cycle for four channels of data takes about 910 microseconds at the nominal 50.4 kHz clock rate. There is no way to terminate a cycle once it is initiated. Loss of clock will cause the conversion cycle power to remain ON once a "Go" signal is received. This can be removed by commanding that PHA (1 or 2) redundant section OFF.

During the cruise phase of the satellite mission, the peak detectors will be powered as part of the LEPT (Low Energy Particle Telescope) mode. These have their own synchronous timing as illustrated in Figure 1. The peak detectors hold the most positive voltage input since the last zero crossing of the analog channel, hesitate for 2 microseconds at the next zero crossing and reset to zero. The experiment data section has 2 microseconds to request a PHA reading by generating a "Go" pulse, after which time the PHA logic maintains the peak values for the duration of the total A/D conversion, nominally 910 microseconds. The only control circuits required for the peak detectors are the "Go" detector, "Set" binary and its "Hold" output. Reset is generated for all peak detectors by any of the five inputs making a negative going zero crossing after exceeding the threshold of its discriminator. Reset also occurs at the end of a conversion cycle when the PHA hold level returns to 0.

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Last modified 6/20/03, Tizby Hunt-Ward
tizby@ftecs.com